1. Field of the Invention
The invention in general relates to integrated circuit memory arrays and more particularly with an apparatus and method of addressing such memory arrays.
2. Statement of the Problem
The invention to be disclosed herein shall be described with respect to an architecture used in random access memories (RAMs) although it is also applicable to other integrated circuit memories. Integrated circuit RAM memories generally contain a two dimensional array of storage cells arranged in rows and columns. A common architecture is to connect all cells in a row to a common row line, often referred to as the "word line" and all cells in a column to a common column line often called the "bit line" or "digit line". In this architecture, the row line provides a signal which enables cells to receive or output a data signal and the column line provides the input or output line on which the signal is transferred. An individual cell is addressed via a row decoder that selects a row to be addressed and a column decoder which selects a column to be addressed, thereby selecting one particular cell at the corresponding row and column location. The cell is read or written to by placing an enable signal on the row line in the row associated with the addressed cell and reading or writing a signal on the column line associated with the addressed cell. Integrated circuit memories are also generally binary logic circuits in which information is stored and transferred as voltages representing complementary logic values that are alternately referred to as "true and false", "logic 1 and logic 0", or "logic high and logic low". Typically a voltage of 5 volts may represent the logic 1 state while a voltage of zero volts represents the logic 0 state. Generally, the row and column addresses are applied to the integrated circuit memory chip on the same address lines and are multiplexed by a row address signal (RAS) and a column address signal (CAS). Generally, it is the convention to use the inverse signals RAS* and CAS*. For example, when RAS* goes from high to low, the signal on the address lines is gated into a row address register, and a row address decoder connected to the register decodes the address signal and enables the addressed row. When CAS* goes from high to low the signals on the address lines are gated into a column address register, and a column address decoder connected to the column address register then connects the addressed column to the input/output line.
As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and circuit performance improves, in particular higher clock speeds are obtainable. However, as more and more individual storage cells are placed unto a single chip, the length of the row and column lines become longer as compared to the size of the individual cell. This increases the capacitance of the system and slows the speed of addressing the cells. As is well known, speed is an important factor in such memories, since the faster the cells can be read, the faster is the computer of which the memory is a part, and the more operations the computer can do. Thus a number of enhancements have been made to RAM architecture to increase the response time. Some enhancements involve increasing the electrical response of the system with sophisticated on-chip amplifiers. Other enhancements involve altering the manner of addressing the cells in the array so that multiple cells may be addressed at the same time. The present invention relates to the latter type of enhancement.
Prior art addressing enhancements are page mode addressing, static column mode addressing, and nibble mode addressing. In page mode addressing, RAS* stays low and CAS* is cycled to gate in a sequence of column addresses. Since RAS* remains low and all cells remain enabled throughout the addressing of the entire sequence, page mode addressing saves the time it takes for RAS* to cycle and the cells in the row to turn on and off, as compared to addressing one cell at a time. Static column mode addressing is similar to page mode addressing except that in this mode CAS* stays low and RAS* cycles. Nibble mode addressing is a multiple-bit addressing mode in which the addressed bit and a set number of bits adjacent the addressed bit are addressed in sequence. These addressing enhancements are generally more efficient if the processing system that addresses the memory generally reads or writes data in blocks that are as about as large or larger than the number of bits addressed in sequence. However, if the processor tends to process data in increments that are smaller than the number of bits in the sequence, then these modes become much less efficient than normal addressing of one cell at a time. Thus there is a need for a mode of addressing that increases the efficiency of the addressing no matter what the size of the data sequences that the processor processes.